Data trasfer instructions of ARM cortex M0/M0+ to memory access through registers.

Memory Accesses register

The Cortex-M0 and Cortex-M0+ processors support a number of memory access instructions, which support various data transfer sizes and addressing modes. The supported data transfer sizes are Word, Half Word, and Byte

Table: Memory access instructions for various transfer sizes

Transfer size Unsigned load     Signed load     Signed/Unsigned store
•Word                 LDR                     LDR                     STR
•Half word         LDRH                  LDRSH               STRH
•Byte                  LDRB                   LDRSB               STRB

For memory read operations, the instruction to carry out single accesses is LDR (load):
Instruction used: LDR/LDRH/LDRB
Function: Read single memory data into register
Syntax: LDR <Rt>, [<Rn>, <Rm>] ; Word read
             LDRH <Rt>, [<Rn>, <Rm>] ; Half-Word read
             LDRB <Rt>, [<Rn>, <Rm>] ; Byte read 

Note:
Rt = memory[Rn + Rm]
Rt, Rn, and Rm are low registers

The Cortex-M processors also support immediate offset addressing modes:
Instruction used: LDR/LDRH/LDRB
Function: Read single memory data into register
Syntax: LDR <Rt>, [<Rn>, #immed5] ; Word read
              LDRH <Rt>, [<Rn>, #immed5] ; Half-Word read
              LDRB <Rt>, [<Rn>, #immed5] ; Byte read

Note:
Rt = memory[Rn + ZeroExtend (#immed5 << 2)] ; Word
Rt = memory[Rn + ZeroExtend(#immed5 << 1)] ; Half word
Rt = memory[Rn + ZeroExtend(#immed5)] ; Byte
Rt and Rn are low registers

The Cortex-M Processors support a useful PC-relative load instruction allowing efficient literal data accesses.
Instruction used:LDR
Function: Read single memory data word into register
Syntax: LDR <Rt>, [PC, #immed8] ; Word read

Note: Rt = memory[WordAligned(PC+4) + ZeroExtend(#immed8 << 2)]
Rt is a low register, and targeted address must be a word-aligned address. The reason for adding 4 is due to the pipelined nature of the processor.
Example:
LDR R0,=0x12345678 ; A pseudo instruction that use literal load to put an immediate data into a register
LDR R0, [PC, #0x40] ; Load a data in current program address with offset of 0x40 into R0
LDR R0, label ; Load a data in current program referenced by label into R0

Instruction used: LDR
Function : Read single memory data word into register
Syntax: LDR <Rt>, [SP, #immed8] ; Word read

Note:
vRt = memory[SP + ZeroExtend(#immed8 << 2)]
vRt is a low registe

The Cortex-M0/M0+ Processor can also sign extend the read data automatically using the LDRSB and LDRSH instructions.
Instruction used: LDRSH/LDRSB
Function: Read single signed memory data into register
Syntax:LDRSH <Rt>, [<Rn>, <Rm>] ; Half-Word read
            LDRSB <Rt>, [<Rn>, <Rm>] ; Byte read

Note:
Rt = SignExtend(memory[Rn + Rm])
Rt, Rn, and Rm are low register

For single data memory writes, the instruction is STR (store):

Instruction used: STR/STRH/STRB
Function: Write single register data into memory
Syntax: STR <Rt>, [<Rn>, <Rm>] ; Word write
              STRH <Rt>, [<Rn>, <Rm>] ; Half-Word write
              STRB <Rt>, [<Rn>, <Rm>] ; Byte write

Note:
memory[Rn + Rm] = Rt
Rt, Rn, and Rm are low registers

Like the load operation, the store operation supports an immediate offset addressing mode:
Instruction used: STR/STRH/STRB
Function: Write single memory data into memory
Syntax: STR <Rt>, [<Rn>, #immed5] ; Word write
              STRH <Rt>, [<Rn>, #immed5] ; Half-Word write
              STRB <Rt>, [<Rn>, #immed5] ; Byte write Note:
memory[Rn + ZeroExtend(#immed5 << 2)] = Rt ; Word
memory[Rn + ZeroExtend(#immed5 << 1)] = Rt ; Half word
memory[Rn + ZeroExtend(#immed5)] = Rt ; Byte
Rt and Rn are low registers