Write assembly code to perform logical operations

; Write assembly code to perform logical operations
;------------------------------------------------------------------
; section 1: Targeted logical instructions are of mainly four type
;     1- Logical (AND, OR, EXOR, & NOT)
;    2- Shift (Arithmetic & Logical)
;     3- Rotate
;    4- Reverse
;---------------------------------------------------------------------
        TTL transfer
        AREA Myprog, CODE, READONLY

ENTRY
        EXPORT main
main
       
        ;Initialize values into R1, and R2
        LDR R1,=0x0F0F0F0F
        LDR R2,=0x12345678
        LDR R3,=0xFEDCBA98
        LDR R4,=0xF0F0F0F0
        LDR R5,=0xFFFF0000
;part 1 logical operations       
        ANDS R3, R3, R1        ;ANDS <Rd>, <Rd>, <Rm>   
        ;Rd = AND(Rd, Rm), APSR.N and APSR.Z update
        ORRS R4, R4, R2        ;ORRS <Rd>, <Rd>, <Rm>   
        ;Rd = OR(Rd, Rm), APSR.N and APSR.Z update
        EORS R5, R5, R1        ;EORS <Rd>, <Rd>, <Rm>   
        ;Rd = XOR(Rd, Rm), APSR.N and APSR.Z update
       
        ;Logical Bitwise Clear
        BICS R1, R1, R2        ;BICS <Rd>, <Rd>, <Rm>   
        ;Rd = AND(Rd, NOT(Rm)), APSR.N and APSR.Z update (0x00000FF0=> 0xFFFFF00F)
       
        ;Logical Bitwise NOT
        MVNS R6, R2            ;MVNS <Rd>, <Rm>       
        ;Rd = NOT(Rm), APSR.N and APSR.Z update
       
        ;Test (bitwise AND) the AND but result is not stored
        TST R7, R2            ;TST <Rn>, <Rm>           
        ;Calculate AND(Rn, Rm), APSR.N and APSR.Z update
       
        LDR R3,=0xF1234560
        LDR R1,=0x01
        LDR R2,=0x04
;Part 2 shift operations
        ; Arithmetic shift operaration 1000 1111 -> 1100 0111
        ;When ASR is used, the MSB of the result is unchanged,
        ;and the Carry flag is updated using the last bit shifted out.
        ASRS R3, R3, R1        ;ASRS <Rd>, <Rd>, <Rm>   
        ;Rd = Rd >> Rm, last bit shift out is copied to
        ;Flags APSR.C, APSR.N and APSR.Z are updated
        ASRS R4, R3,#0x04    ;ASRS <Rd>, <Rm>, #immed5
        ;Rd = Rm >> immed5, last bit shifted out is copied to
        ;APSR.C, APSR.N and APSR.Z are also updated.
       
        ;Logical shift operations
        LSLS R3, R3, R1        ;LSLS <Rd>, <Rd>, <Rm>   
        ;Rd = Rd << Rm, last bit shifted out is copied to
        ;APSR.C, APSR.N and APSR.Z are also updated
        LSLS R5, R3, #0x01    ;LSLS <Rd>,<Rm>,#immed5
        ;Rd = Rm << #immed5, last bit shifted out is copied to
        ;APSR.C, APSR.N and APSR.Z are also updated
        LSRS R3, R3, R2        ;LSRS <Rd>, <Rd>, <Rm>   
        ;Rd = Rd >> Rm, last bit shifted out is copied to
        ;APSR.C, APSR.N and APSR.Z are also updated
        LSRS R7, R3,#0x01    ;LSRS <Rd>,<Rm>,#immed5   
        ;Rd = Rm >> #immed5, last bit shifted out is copied to
        ;APSR.C, APSR.N and APSR.Z are also updated

        ;0001 1010 shift right by 2 times -> 0000 0110
       
;Part 3 rotate operation
        RORS R3, R3, R2        ;RORS <Rd>, <Rd>, <Rm>   
        ;Rd = Rd rotate right by Rm bits, last bit shifted out is
        ;copied to APSR.C, APSR.N and APSR.Z are also updated
       
        ;0001 1010 4 time rotate to right -> 1010 0001
       
        LDR R4,=0x56789ABC
        LDR R3,=0x12345678
;Part 4 reverse operations
        REV R7, R4            ;REV <Rd>, <Rm>           
        ;Rd = {Rm[7:0], Rm[15:8], Rm[23:16], Rm[31:24]}
        REV16 R6, R3        ;REV16 <Rd>, <Rm>       
        ;Rd = {Rm[23:16], Rm[31:24], Rm[7:0] , Rm[15:8]}
        REVSH R5, R4        ;REVSH <Rd>, <Rm>       
        ;Rd = SignExtendof 7 to [16:31],({Rm[7:0] , Rm[15:8]})

done
        SWI &11            ; Call system interrupt to end the program
        END