;Write assembly language code for all type of the conditional and
;unconditional program flow control instructions.
; 1- unconditional jump
; 2- conditional jump
; 2.1 - signed and unsigned conditional jump based on comperision
; 2.2 - signed and unsigned conditional jump based on overflow
; 2.3 - signed conditional jump based on N flag
TTL transfer
AREA Myprog, CODE, READONLY
ENTRY
EXPORT main
main
;************************unconditional branch*****************************************
;Table 1: branch instructions with ranges
;==============================================================================
;Branch range Available instruction
;==============================================================================
;Under +/–254 bytes B label
; B<cond> label
;Under +/–2 KB B label
;Under +/–16 MB BL label
;Over +/–16 MB LDR R0, =label ; Load the address value of label in R0
; BX R0; Branch to address pointed to by R0, or
; BLX R0; Branch to address pointed to by R0 and update LR
;==============================================================================
B LOAD_R2 ; B to the label
load_return
;Branch and link with updated value of LR = R14
BL LOAD_ADD1 ;branch and updated PC link to the LR(R14), return to the next instruction
; address of MOVS R1,#3 will store into the LR for return
MOVS R1,#3
MOVS R2,#3
MOVS R3,#4
;*****************************conditional instructions***************************
;Table2: Conditional branch instructions for value comparison operations
;=============================================================================
;Required branch control Unsigned data Signed data
;=============================================================================
;If (R0 equal R1) then branch BEQ label BEQ label
;If (R0 not equal R1) then branch BNE label BNE label
;If (R0 > R1) then branch BHI label BGT label
;If (R0 >= R1) then branch BCS label/BHS label BGE label
;If (R0 < R1) then branch BCC label/BLO label BLT label
;If (R0 <= R1) then branch BLS label BLE label
;=============================================================================
;for signed and unsigned equ and Not equ
CMP R2, R1 ; compare the R2 with R1 and reflect the status in FLAGS
BEQ LOOP3 ;branch if R2 = R1
LOOP3 CMP R2,R3 ; compare the R2 with R3 and reflect the status in FLAGS
BNE LOOP4_1 ; branch if R2 != R3
;unsigned greater than/equal and less than/equal
LOOP4_1 MOVS R1,#5 ;Loop counter starting value is 5
LOOP4
ADDS R4, #1
CMP R1, R4
BLO LOOP5 ;branch if R1<R4/ R1 is lower than R4
SUBS R1, #1
BHI LOOP4 ;branch if R1 is higher than 1
LOOP5 MOVS R1,#6 ;Loop counter starting value is 6
ADDS R4, #1
CMP R1, R4
BLS LOOP6 ;branch if R1<= R4/ R1 lower than or same to R4
SUBS R1, #1
BHS LOOP5 ;branch if R1 is higher and same to 1
;signed greater than/equal and less than/equal
LOOP6 MOVS R1,#5 ;Loop counter starting value is 5
MOVS R4,#0 ;Set R4 to zero
LOOP7
ADDS R4, #1
CMP R1, R4
BLT LOOP8 ;branch if R1<R4
SUBS R1, #1
BGT LOOP7 ;branch if R1>1
LOOP8 MOVS R1,#6 ;Loop counter starting value is 3
ADDS R4, #1
CMP R1, R4
BLE LOOP9 ; branch if R1<=R4
SUBS R1, #1
BGE LOOP8 ; branch if R1>=1
;Table3: Conditional branch instructions for overflow detections
;==============================================================================
;Required branch control Unsigned data Signed data
;==============================================================================
;If (overflow(R0 + R1)) then branch BCS label BVS label
;If (no_overflow(R0 + R1)) then branch BCC label BVC label
;If (overflow(R0 – R1)) then branch BCC label BVS label
;If (no_overflow(R0 – R1)) then branch BCS label BVC label
;==============================================================================
;Table4: Conditional branch instructions for positive or negative value detection
;==============================================================================
;Required branch control Unsigned data Signed data
;==============================================================================
;If (result >=0) then branch Not applicable BPL label
;If (result < 0) then branch Not applicable BMI label
;==============================================================================
;unsigned overflow detection/ carry flag based branch
LOOP9
LDR R6,=0xFFFFFFFF
LDR R5,=0x00000001
LOOP11 ADDS R6,R6,R5
; during first addition carry flag is set, ans is C=1 R6=0x00000000
; during second addition carry flag is reset, ans is C=0 R6=0x00000001
BCC LOOP10 ;branch if C=0
BCS LOOP11 ;branch if C=1
;above example peform the overflow for addition operations
;for subtraction you can do it by your own
;Signed overflow incorporate signed ov, carry and Signed flag
LOOP10
LDR R6,=0xFFFFFFFF
LDR R5,=0x80000000
LOOP12 ADDS R6,R6,R5
; during first addition sign change and ov flag is set, ans is N=0,C=1,ov=1 R6=0x7FFFFFFF
; during second addition sign changes and ov flag is reset, ans is N=1,C=0,ov=0 R6=0xFFFFFFFF
BVC LOOP13 ;branch if V=0
BCS LOOP15 ;branch if C=1
LOOP15 BPL LOOP16 ;branch if N=0
LOOP16 BVS LOOP12 ;branch if V=1
LOOP13 BCC LOOP14 ;branch if C=0
LOOP14 BMI LOOP17 ;branch if N=1
LOOP17 B done
LOAD_R2
MOVS R2,#0X04
LDR R0,=load_return ; psudo load value of label into the R0 for BX instruction
BX R0 ; unconditional return through branch and exchange
;loop inside the loop
;use of BLX and BL with <Rm>
LOAD_ADD1
MOV R1,R14 ;Storing the LR(R14) value into R1 for further use
LDR R2,=load
BLX R2 ;Jump to the PC where R2 is pointing and update LR with new value
LDR R3,=add2
BLX R3 ;Jump to the PC where R3 is pointing and update LR with new value
BX R1 ;Return from original location/ return to the line BL LOAD_ADD1
;load subroutine
load LDR R6,=0x034
LDR R7,=0x235
BX LR ; return to the line next to BLX R2
;add subroutine
add2 ADDS R6, R7, R6
BX LR ; return to the line next to BLX R3
done
SWI &11
END
Write assembly language code for all type of the conditional and unconditional program flow control instructions.
Write assembly code to perform Arithmetic operations
;------------------------------------------------------------------
; section 1: Targeted arithmetic instructions are of mainly four type
; 1- Addition
; 2- Subtraction
; 3- Multiplication
; 4- Comparision
;---------------------------------------------------------------------
TTL transfer
AREA Myprog, CODE, READONLY
ENTRY
EXPORT main
main
;Initialize values into R1, and R2
LDR R1,=0xFA
LDR R2,=0x15
;part 1 Addition operations
;Three operand arithmetic instructions
ADD R2,R1,R2 ;ADDS <Rd>, <Rn>, <Rm>
;Rd = Rn + Rm, APSR update
ADDS R3,R1,#0x07 ;ADDS <Rd>, <Rn>, #immed3
;Rd = Rn + ZeroExtend(#immed3), APSR update
ADDS R3,#0xFF ;ADDS <Rd>, #immed8
;Rd = Rd + ZeroExtend(#immed8), APSR update
ADD R4,R2 ;ADD <Rd>, <Rm>
;Rd = Rd + Rm
;Arithmetic operations with SP
ADD R3, SP, R3 ;ADD <Rd>, SP, <Rd>
;Rd = Rd + SP
ADD SP, R2 ;ADD SP, <Rm>
;SP = SP + Rm
ADD R2, SP, #0x04 ;ADD <Rd>, SP, #immed8
;Rd = SP + ZeroExtend (#immed8)
ADD SP, SP, #0x08 ;ADD SP, SP, #immed7
;SP = SP + ZeroExtend(#immed7)
;Arithmetic operations with PC
ADD R2, PC, #0x04 ;ADD <Rd>, PC, #immed8
;Rd = PC[31:0] + ZeroExtend(#immed8 << 2).
;Arithmetic operations with carry
ADCS R3, R2 ;ADCS <Rd>, <Rm>
;Rd = Rd + Rm + Carry.
;Part 2 Subtraction oprtations
;Three operand arithmatic instructions
SUBS R5, R1, R2 ;SUBS <Rd>, <Rn>, <Rm>
;Rd = Rn – Rm, APSR update
SUBS R5, R1, #0x07 ;SUBS <Rd>, <Rn>, #immed3
;Rd = Rn – ZeroExtend(#immed3), APSR update.
SUBS R5, #0x01 ; SUBS <Rd>, #immed8
;Rd = Rd – ZeroExtend(#immed8), APSR update.
;Arithmetic operations with SP
SUB SP, SP, #0x04 ;SUB SP, SP, #immed7
;SP = SP – ZeroExtend(#immed7)
;Arithmetic operations with carry
SBCS R6, R6, R2 ;SBCS <Rd>, <Rd>, <Rm>
;Rd = Rd – Rm – Borrow, APSR update
;Reverse Subtract
RSBS R7, R1, #0x00 ;RSBS <Rd>, <Rn>, #0
;Rd = 0 – Rm, APSR update
;part 3 multiplication
;Multiply
MULS R7, R1, R7 ;MULS <Rd>, <Rm>, <Rd>
;Rd = Rd * Rm, APSR.N and APSR.Z
;part 4 comparision
;Compare by subtraction but result is not stored
;Rm >Rn C =0, Z =0
;Rm <Rn C =1, Z =0
;Rm =Rn C =0, Z =1
CMP R1, R2 ;CMP <Rn>, <Rm>
;Calculate Rm – Rn, APSR update
CMP R2, #0x04 ;CMP <Rn>, #immed8
; ZeroExtended(#immed8) – Rd , APSR update
CMN R1, R2 ;CMN <Rn>, <Rm>
;Compare negative, Calculate NEG(Rm) – Rn , APSR update
done
SWI &11 ; Call system interrupt to end the program
END
Write assembly code to perform logical operations
; Write assembly code to perform logical operations
;------------------------------------------------------------------
; section 1: Targeted logical instructions are of mainly four type
; 1- Logical (AND, OR, EXOR, & NOT)
; 2- Shift (Arithmetic & Logical)
; 3- Rotate
; 4- Reverse
;---------------------------------------------------------------------
TTL transfer
AREA Myprog, CODE, READONLY
ENTRY
EXPORT main
main
;Initialize values into R1, and R2
LDR R1,=0x0F0F0F0F
LDR R2,=0x12345678
LDR R3,=0xFEDCBA98
LDR R4,=0xF0F0F0F0
LDR R5,=0xFFFF0000
;part 1 logical operations
ANDS R3, R3, R1 ;ANDS <Rd>, <Rd>, <Rm>
;Rd = AND(Rd, Rm), APSR.N and APSR.Z update
ORRS R4, R4, R2 ;ORRS <Rd>, <Rd>, <Rm>
;Rd = OR(Rd, Rm), APSR.N and APSR.Z update
EORS R5, R5, R1 ;EORS <Rd>, <Rd>, <Rm>
;Rd = XOR(Rd, Rm), APSR.N and APSR.Z update
;Logical Bitwise Clear
BICS R1, R1, R2 ;BICS <Rd>, <Rd>, <Rm>
;Rd = AND(Rd, NOT(Rm)), APSR.N and APSR.Z update (0x00000FF0=> 0xFFFFF00F)
;Logical Bitwise NOT
MVNS R6, R2 ;MVNS <Rd>, <Rm>
;Rd = NOT(Rm), APSR.N and APSR.Z update
;Test (bitwise AND) the AND but result is not stored
TST R7, R2 ;TST <Rn>, <Rm>
;Calculate AND(Rn, Rm), APSR.N and APSR.Z update
LDR R3,=0xF1234560
LDR R1,=0x01
LDR R2,=0x04
;Part 2 shift operations
; Arithmetic shift operaration 1000 1111 -> 1100 0111
;When ASR is used, the MSB of the result is unchanged,
;and the Carry flag is updated using the last bit shifted out.
ASRS R3, R3, R1 ;ASRS <Rd>, <Rd>, <Rm>
;Rd = Rd >> Rm, last bit shift out is copied to
;Flags APSR.C, APSR.N and APSR.Z are updated
ASRS R4, R3,#0x04 ;ASRS <Rd>, <Rm>, #immed5
;Rd = Rm >> immed5, last bit shifted out is copied to
;APSR.C, APSR.N and APSR.Z are also updated.
;Logical shift operations
LSLS R3, R3, R1 ;LSLS <Rd>, <Rd>, <Rm>
;Rd = Rd << Rm, last bit shifted out is copied to
;APSR.C, APSR.N and APSR.Z are also updated
LSLS R5, R3, #0x01 ;LSLS <Rd>,<Rm>,#immed5
;Rd = Rm << #immed5, last bit shifted out is copied to
;APSR.C, APSR.N and APSR.Z are also updated
LSRS R3, R3, R2 ;LSRS <Rd>, <Rd>, <Rm>
;Rd = Rd >> Rm, last bit shifted out is copied to
;APSR.C, APSR.N and APSR.Z are also updated
LSRS R7, R3,#0x01 ;LSRS <Rd>,<Rm>,#immed5
;Rd = Rm >> #immed5, last bit shifted out is copied to
;APSR.C, APSR.N and APSR.Z are also updated
;0001 1010 shift right by 2 times -> 0000 0110
;Part 3 rotate operation
RORS R3, R3, R2 ;RORS <Rd>, <Rd>, <Rm>
;Rd = Rd rotate right by Rm bits, last bit shifted out is
;copied to APSR.C, APSR.N and APSR.Z are also updated
;0001 1010 4 time rotate to right -> 1010 0001
LDR R4,=0x56789ABC
LDR R3,=0x12345678
;Part 4 reverse operations
REV R7, R4 ;REV <Rd>, <Rm>
;Rd = {Rm[7:0], Rm[15:8], Rm[23:16], Rm[31:24]}
REV16 R6, R3 ;REV16 <Rd>, <Rm>
;Rd = {Rm[23:16], Rm[31:24], Rm[7:0] , Rm[15:8]}
REVSH R5, R4 ;REVSH <Rd>, <Rm>
;Rd = SignExtendof 7 to [16:31],({Rm[7:0] , Rm[15:8]})
done
SWI &11 ; Call system interrupt to end the program
END
Data trasfer instructions of ARM cortex M0/M0+ to memory access through registers.
Memory Accesses register
The Cortex-M0 and Cortex-M0+ processors support a number of memory access instructions, which support various data transfer sizes and addressing modes. The supported data transfer sizes are Word, Half Word, and Byte
Table: Memory access instructions for various transfer sizes
Transfer size Unsigned load Signed load Signed/Unsigned store
•Word LDR LDR STR
•Half word LDRH LDRSH STRH
•Byte LDRB LDRSB STRB